1. Technical Field
The disclosure relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
A conventional semiconductor memory apparatus includes a great number of memory cells, and is configured to store data in the memory cells. A conventional semiconductor memory apparatus includes a plurality of mats each of which is a set of memory cells, and is designed in such a manner that an address signal is used to select the location of a mat (memory cells) in which data are to be stored. Furthermore, the semiconductor memory apparatus includes extra mats to replace a mat having a failed memory cell, and is designed in such a manner that when an address signal is inputted to store data in the mat having the failed memory cell, an extra mat is internally selected to store data according to the address signal.
When an address signal is inputted to designate the location of a mat having a failed memory cell, that is, a mat in which a fail occurs, a circuit included in the semiconductor memory apparatus designates the storage location of data in an extra mat instead of the mat in which the fail occurred. Such an operation is referred to as a redundancy operation.
FIG. 1 is an illustration of a conventional semiconductor memory apparatus which includes a redundancy signal generation unit 10 and first to sixteenth mat control signal generation units 101 to 116.
The redundancy signal generation unit 10 has mat information set by fuse cutting, and is configured to compare address information ADDRESS with the mat information and enable one of first to sixteenth redundancy signals XHITB<0:15> to a low level. The fuse cutting information can be address information of a mat in which a fail occurs and which is set by fuse cutting. Furthermore, a mat can be the unit of a data storage area in which data is stored, and the mat information set by fuse cutting is information of a mat in which a fail occurs.
Each of the first to sixteenth mat control signal generation units 101 to 116 is configured to receive mat address signals ADD_mat<0:3> in which addresses having mat information in the address information ADDRESS are pre-decoded. Furthermore, the first to sixteenth mat control signal generation units 101 to 116 receive the first to sixteenth redundancy signals XHITB<0:15>, respectively. For example, the first mat control signal generation unit 101 receives the mat address signals ADD_mat<0:3> and the first redundancy signal XHITB<0>.
The operations of the first to sixteenth mat control signal generation units 101 to 116, which are performed in response to the mat address signals ADD_mat<0:3> and the corresponding redundancy signal XHITB<i>, are identical to each other. Therefore, the operation of the first mat control signal generation unit 101 will be described as a representative example.
When the first redundancy signal XHITB<0> is enabled to a low level, the first mat control signal generation 101 enables a first mat control signal Mat_ctrl regardless of the mat address signals ADD_mat<0:3>.
The semiconductor memory apparatus operating in such a manner includes the 16 mat control signal generation units 101 to 116 to control 16 mats, and each of the mat control signal generation units receives one redundancy signal XHITB<i> and four mat address signals ADD_mat<0:3>.
A problem with conventional semiconductor memory apparatus is inefficency. As the number of mats to be controlled increases, the number of mat control signal generation units increases. Accordingly, the number of signal lines for transferring signals inputted to the mat control signal generation units also increases. Therefore, it is desired to increase the area efficiency of the semiconductor memory apparatus by reducing the number of signals inputted to the mat control signal generation units to decrease the number of signal lines.